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73004 jo im no.7851-1/25 LC87F54C8A overview the LC87F54C8A is 8-bit single chip microcontroller with the following one-chip features : ? cpu : operable at a minimum bus cycle time of 100ns ? on-chip flash rom capacity : 128k bytes (on-board rewritable) ? on-chip ram capacity : 4k bytes ? two high performance 16-bit timer/counters (can be divided into 8-bit timers) ? four 8-bit timers with prescalers ? timer for use as date/time clock ? two synchronous serial i/o ports (with au tomatic block transmit/receive function) ? one asynchronous/synchronous serial i/o port ? 12-bit pwm 2 ? 12-channel 8-bit ad converter ? high speed 8-bit parallel interface ? high speed clock counter ? system clock divider ? 21-source 10-vectored interrupt system features read only memory (flash rom) ? single 5v power supply, on-board writeable ? block erase in 128 byte units ? 131071 8 bits (LC87F54C8A) bus cycle time ? 100ns (10mhz) note : bus cycle time indicates the speed to read rom. minimum instruction cycle time (tcyc) ? 300ns (10mhz) ordering number : enn7851 cmos ic from 128k-byte, ram 4k-byte on chip 8-bit 1-chip microcontroller ver.1.00
LC87F54C8A no.7851-2/25 ports ? input/output ports input/output programmable for each bit individually 59 (p1n, p2n, p3n, p70 to p73, p8n, pan, pbn, pcn, s2pn) data direction programmable in nibble units 8 (p0n) ? input ports 2 (xt1, xt2) ? pwm output ports 2 (pwm0, pwm1) ? oscillator pins 2 (cf1, cf2) ? reset pin 1 (res ) ? power supply 8 (v ss 1 to 3, v dd 1 to 3) timer ? timer 0 : 16-bit timer/counter with capture register mode 0 : two 8-bit timers with programmable 8-bit prescaler and 8-bit capture register mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit counter with 8-bit capture register mode 2 : 16-bit timer with 8-bit programma ble prescaler and 16-bit capture register mode 3 : 16-bit counter with 16-bit capture register ? timer 1 : pwm/16-bit timer/counter with toggle output mode 0 : 8-bit timer (with toggle output) + 8-bit timer/counter (with toggle output) mode 1 : two 8-bit pwm mode 2 : 16-bit timer/counter (with toggle output) toggle output is also possible by using the lower order 8-bits mode 3 : 16-bit timer (with toggle output) the lower order 8 bits can be used as pwm output. ? timer 4 : 8-bit timer with 6-bit prescaler ? timer 5 : 8-bit timer with 6-bit prescaler ? timer 6 : 8-bit timer with 6-bit prescaler ? timer 7 : 8-bit timer with 6-bit prescaler ? base timer 1. clock for the base timer is selectable from sub- clock (32.768khz crystal oscillation), system clock or programmable prescaler output of timer 0. 2. there can be five separate interrupt sources. high speed clock counter 1. maximum of 20mhz possible (when using a 10mhz main clock). 2. real-time output. serial interface ? sio0 : 8-bit synchronous serial interface 1. lsb first/msb first-function available 2. an internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 256 bits) ? sio1 : 8-bit asynchronous/synchronous serial interface mode 0 : synchronous 8-bit serial i o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1 : asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud-rate 8 to 2048 tcyc) mode 2 : bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3 : bus mode 2 (start detection, 8 data bits, stop detection) ? sio2 : 8-bit synchronous serial interface 1. lsb-first 2. internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tcyc) 3. consecutive automatic data communication (1 to 32 bytes)
LC87F54C8A no.7851-3/25 ad converter ? 12-channel 8-bit ad converter pwm ? 2 channel synchronous variable 12 bit pwm parallel interface ? rs, rd , wr , cs0 to cs2 outputs (polarity can be toggled) ? read/write possible in 1 tcyc remote receiver circuit (share with p73/int3/t0in terminal) ? noise rejection function (the filtering time of the noise rejection filter (1 tcyc/32 tcyc /128 tcyc) can be switched by program.) watchdog timer ? external rc circuit is required. ? interrupt or system reset is activated when the timer overflows. interrupts ? 21-source and 10-vectored interrupt function : 1. three interrupt priorities, low (l), high (h) and highest (x) are supported with multi-level nesting possible. during interrupt handling, an equal or lower level interrupt request is refused. 2. if interrupt requests for two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1/sio2 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority level : x > h > l ? for equal priority levels, vector with lowest address takes precedence. subroutine stack levels ? a maximum of 2048 levels (set stack inside ram) multiplication and division ? 16-bits 8-bits (5 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) ? 16-bits 8-bits (8 instruction-cycle times) ? 24-bits 16-bits (12 instruction-cycle times) oscillation circuits ? built-in rc oscillation circuit used for the system clock ? cf oscillation circuit used for the system clock ? crystal oscillation circuit used for the system clock system clock divider ? operable on the lowest power consumption ? minimum instruction cycle time 300ns, 600ns, 1.2 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10mhz main clock)
LC87F54C8A no.7851-4/25 standby function ? halt mode the halt mode stops program execution while the peripheral circuits keep operating and minimizes power consumption. this operation mode can be released by a system reset or an interrupt request. ? hold mode the hold mode stops program execution and all oscill ation circuits : cf, rc and crystal oscillations. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal (res ) 2. supply the selected level to at leas e one of int0, int1, int2, int4, int5. 3. supply an interrupt condition to port 0. ? x?tal hold mode the x?tal hold mode stops program execution and all peripheral circuits except for the base timer. the crystal oscillator maintains its state at hold mode inception. this mode can be released by the following conditions. 1. supply "l" level to the reset terminal ( res ). 2. supply the selected level to at leas t one of int0, int1, int2, int4, int5 3. supply an interrupt condition to port 0. 4. supply an interrupt condition to the base timer circuit. shipping form ? qfp80e ? tqfp80 development tools ? evaluation (eva) chip : lc876093 ? emulator : eva62s + ecb876600a + sub875400 + pod80qfp or pod80sqfp ? flash rom writer adapter : w87f54256q (qip80e), w87f54256sq (tqfp80) package dimensions package dimensions unit : mm unit : mm 3174a 3298
LC87F54C8A no.7851-5/25 pin assignment LC87F54C8A qip80e top view pb5/d5 pb6/d6 pb7/d7 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07 p06 p05 p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/do2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33 p32 p31 p30 pb4/d4 pb3/d3 pb2/d2 pb1/d1 pb0/d0 v ss 3 v dd 3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pa0/cs2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pa1/cs1 pa2/cs0 pa3/wr pa4/rd pa5/rs p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pa3/wr pa4/rd pa5/rs p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 60 5 9 5 8 57 5 6 55 54 5 3 5 2 5 1 5 0 4 9 4 8 47 4 6 45 44 4 3 4 2 4 1 pb7/d7 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07 p06 p05 p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33 p32 p31 p30 p87/an7 p86/an6 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pb6/d6 pb5/d5 pb4/d4 pb3/d3 pb2/d2 pb1/d1 pb0/d0 v ss 3 v dd 3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pa0/cs2 pa1/cs1 pa2/cs0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC87F54C8A tqfp80 1 2 3 4 5 6 7 8 9 top view
LC87F54C8A no.7851-6/25 pad coordinate values qip name tqfp qip name tqfp 1 pa1/cs1 79 41 si2p3/sck20 39 2 pa2/cs0 80 42 pwm1 40 3 pa3/wr 1 43 pwm0 41 4 pa4/rd 2 44 v dd 2 42 5 pa5/rs 3 45 v ss 2 43 6 p70/int0/t0lcp/an8 4 46 p00 44 7 p71/int1/t0hcp/an9 5 47 p01 45 8 p72/int2/t0in 6 48 p02 46 9 p73/int3/t0in 7 49 p03 47 10 res 8 50 p04 48 11 xt1/an10 9 51 p05 49 12 xt2/an11 10 52 p06 50 13 v ss 1 11 53 p07 51 14 cf1 12 54 p20/int4/t1in 52 15 cf2 13 55 p21/int4/t1in 53 16 v dd 1 14 56 p22/int4/t1in 54 17 p80/an0 15 57 p23/int4/t1in 55 18 p81/an1 16 58 p24/int5/t1in 56 19 p82/an2 17 59 p25/int5/t1in 57 20 p83/an3 18 60 p26/int5/t1in 58 21 p84/an4 19 61 p27/int5/t1in 59 22 p85/an5 20 62 pb7/d7 60 23 p86/an6 21 63 pb6/d6 61 24 p87/an7 22 64 pb5/d5 62 25 p30 23 65 pb4/d4 63 26 p31 24 66 pb3/d3 64 27 p32 25 67 pb2/d2 65 28 p33 26 68 pb1/d1 66 29 p34 27 69 pb0/d0 67 30 p10/so0 28 70 v ss 3 68 31 p11/si0/sb0 29 71 v dd 3 69 32 p12/sck0 30 72 pc7/a7 70 33 p13/so1 31 73 pc6/a6 71 34 p14/si1/sb1 32 74 pc5/a5 72 35 p15/sck1 33 75 pc4/a4 73 36 p16/t1pwml 34 76 pc3/a3 74 37 p17/t1pwmh/buz 35 77 pc2/a2 75 38 si2p0/so2 36 78 pc1/a1 76 39 si2p1/si2/sb2 37 79 pc0/a0 77 40 si2p2/sck2 38 80 pa0/cs2 78
LC87F54C8A no.7851-7/25 system block diagram interru p t control cf standb y control rc xtal clock generator ir pl a flash rom pc sio0 sio1 timer 0 timer 1 bus interface port 1 port 0 port 7 port 8 adc port 2 int4, 5 parallel interface port a port b port c acc b re g iste r c re g iste r psw rar ram stack pointe r watch do g timer pwm0 pwm1 base timer alu int0 to 3 noise rejection filter sio2 timer 4 timer 5 port 3 timer 6 timer 7
LC87F54C8A no.7851-8/25 pin description pin name i/o function option v ss 1, v ss 2, v ss 3 - power terminal (-) no v dd 1, v dd 2, v dd 3 - power terminal (+) no port 0 p00 to p07 i/o ? 8-bit input/output port ? data direction programmable in nibble units ? pull-up resistor provided/not provided (specified in nibble units) ? hold release input ? port 0 interrupt input yes port 1 p10 to p17 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p10 : sio0 data output p11 : sio0 data input, bus input/output p12 : sio0 clock input/output p13 : sio1 data output p14 : sio1 data input, bus input/output p15 : sio1 clock input/output p16 : timer 1 pwml output p17 : timer 1 pwmh output/buzzer output yes port 2 ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p20 to p23 : int4 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input p24 to p27 : int5 input/hold release input/timer 1 event input/timer 0l capture input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int4 enable enable enable disable disable int5 enable enable enable disable disable p20 to p27 i/o yes port 3 p30 to p34 i/o ? 5-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) yes port 7 ? 4-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions p70 : int0 input/hold release input/timer 0l capture input/output for watchdog timer p71 : int1 input/hold release input/timer 0h capture input p72 : int2 input/hold release input/timer 0 event input/timer0l capture input p73 : int3 input with noise filter/timer 0 event input/timer 0h capture input ? interrupt detection style rising falling rising/ falling h level l level int0 enable enable disable enable enable int1 enable enable disable enable enable int2 enable enable enable disable disable int3 enable enable enable disable disable p70 to p73 i/o ? ad converter input port : an8 (p70), an9 (p71) no continued on next page.
LC87F54C8A no.7851-9/25 continued from preceding page. pin name i/o function option port 8 p80 to p87 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? other functions p80 to p87 : ad converter input port no port a pa0 to pa5 i/o ? 6-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pa0 : parallel interface output cs2 pa1 : parallel interface output cs1 pa2 : parallel interface output cs0 pa3 : parallel interface output wr pa4 : parallel interface output rd pa5 : parallel interface output rs yes port b pb0 to pb7 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pb0 to pb7 : parallel interface data input/output, address output yes port c pc0 to pc7 i/o ? 8-bit input/output port ? data direction programmable for each bit individually ? pull-up resistor provided/not provided (specified by bit) ? other functions pc0 to pc7 : parallel interface address output yes sio2 port si2p0 to si2p3 i/o ? 4-bit input/output port ? data direction programmable for each bit individually ? other functions si2p0 : sio2 data output si2p1 : sio2 data input, bus input/output si2p2 : sio2 clock input/output si2p3 : sio2 clock output no pwm0 o pwm0 output port no pwm1 o pwm1 output port no res i reset terminal no xt1 i ? input terminal for 32.768khz x'tal oscillation ? other function an10 : ad converter input port general input port when not in use, connect terminal to v dd 1. no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? other function an11 : ad converter input port general input port when not in use, set as oscillation and leave terminal open no cf1 i input terminal for ceramic resonator no cf2 o output terminal for ceramic resonator no
LC87F54C8A no.7851-10/25 port output configuration output configuration and pull-up resistor options are shown in the following table. input is possible even when a port is in output mode. terminal option applies to : option output format pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 p20 to p27 p30 to p36 each bit 2 nch-open drain programmable 1 cmos programmable pa0 to pa5 pb0 to pb7(*) pc0 to pc7 each bit 2 nch-open drain programmable p70 - none nch-open drain programmable p71 to p73 - none cmos programmable p80 to p87 - none nch-open drain none si2p0, si2p2 si2p3 pwm0, pwm1 - none cmos none si2p1 - none cmos (when used as general port) nch-open drain (when used for sio2 data) none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation none note 1 : programmable pull-up resistor of port 0 is specified in nibble units (p00 to p03, p04 to p07). ( * ) when in parallel interface mode, pb0 to pb7 output format is cmos, regardless of any selected option. note : to reduce v dd signal noise and to increase the duration of the backup battery supply, v ss 1, v ss 2 and v ss 3 should connect to each other and they should also be grounded. example 1 : during backup in hold mode, port output "h" level is supplied from the back-up capacitor. continued on next page. power supply v ss 1 back-up capacitor v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
LC87F54C8A no.7851-11/25 continued from preceding page. example 2 : during backup in hold mode, output is not held high and its value in unsettled. power supply v ss 1 back-up capacitor v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
LC87F54C8A no.7851-12/25 absolute maximum ratings / ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1 = v dd 2 = v dd 3 -0.3 +6.5 input voltage v i (1) xt1, xt2, cf1 -0.3 v dd +0.3 output voltage v o (1) pwm0, pwm1 -0.3 v dd +0.3 input/output voltage v io (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c ? si2p00 to si2p03 ? pwm0, pwm1 -0.3 v dd +0.3 v ioph(1) ? ports 0, 1, 2, 3 ? ports a, b, c ? si2p00 to si2p03 ? pwm0, pwm1 ? cmos output ? for each pin. -10 peak output current ioph(2) p71 to p73 for each pin. -5 ioah(1) p71 to p73 total of all pins -5 ioah(2) ? port 1 ? pwm0, pwm1 ? port 3 ? si2p00 to si2p03 total of all pins -30 ioah(3) ports 0, 2 total of all pins -20 ioah(4) port b total of all pins -20 high level output current total output current ioah(5) ports a, c total of all pins -20 iopl(1) ? p02 to p07 ? ports 1, 2, 3 ? ports a, b, c ? si2p00 to si2p03 ? pwm0, pwm1 for each pin. 20 iopl(2) p00, p01 for each pin. 30 peak output current iopl(3) ports 7, 8 for each pin. 5 ioal(1) port 7 total of all pins 15 ioal(2) port 8 total of all pins 15 ioal(3) ? port 1 ? pwm0, pwm1 ? port 3 ? si2p00 to si2p03 total of all pins 50 ioal(4) ports 0, 2 total of all pins 70 ioal(5) port b total of all pins 40 low level output current total output current ioal(6) ports a, c total of all pins 40 ma qip80e 395 maximum power consumption pd max tqfp80 ta = -20 to +70c 343 mw operating temperature range topr -20 70 storage temperature range tstg -55 125 c
LC87F54C8A no.7851-13/25 recommended operating range / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit 0.294 s tcyc 200 s 4.5 5.5 operating supply voltage range v dd (1) v dd 1 = v dd 2 = v dd 3 0.588 s tcyc 200 s except for on-board rewriting 2.5 5.5 hold voltage vhd v dd 1 = v dd 2 = v dd 3 ram and register data are kept in hold mode. 2.0 5.5 v ih (1) ? ports 1, 2 ? si2p00 to 03 ? p71 to p73 ? p70 port input/interrupt 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) ? ports 0, 8, 3 ? ports a, b, c 2.5 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer 2.5 to 5.5 0.9v dd v dd input high voltage v ih (4) xt1, xt2, cf1, res 2.5 to 5.5 0.75v dd v dd v il (1) ? ports 1, 2 ? si2p00 to 03 ? p71 to p73 ? p70 port input/interrupt 2.5 to 5.5 v ss 0.1v dd +0.4 v il (2) ? ports 0, 8, 3 ? ports a, b 2.5 to 5.5 v ss 0.15v dd +0.4 v il (3) port 70 watchdog timer 2.5 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (4) xt1, xt2, cf1, res 2.5 to 5.5 v ss 0.25v dd v 4.5 to 5.5 0.294 200 operation cycle time tcyc except for on-board rewriting 2.5 to 5.5 0.588 200 s ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty = 505% 4.5 to 5.5 0.1 10 ? leave cf2 pin open ? system clock divider set to 1/1 ? external clock duty = 505% 2.5 to 5.5 0.1 5 ? leave cf2 pin open ? system clock divider set to 1/2 4.5 to 5.5 0.2 20.4 external system clock frequency fexcf(1) cf1 ? leave cf2 pin open ? system clock divider set to 1/2 2.5 to 5.5 0.1 10 fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 10 fmcf(2) cf1, cf2 5mhz ceramic resonator oscillation refer to figure 1 2.5 to 5.5 5 fmrc rc oscillation 2.5 to 5.5 0.3 2.0 mhz oscillation frequency range (note1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 to 5.5 32.768 khz note 1 : the oscillation parameters are shown on tables 1 and 2. note 2 : v dd 4.5v is required for on-board flash rom rewriting.
LC87F54C8A no.7851-14/25 electrical characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c ? si2p00 to si2p03 ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in = v dd (including the off-leak current of the output tr.) 2.5 to 5.5 1 i ih (2) xt1, xt2 ? using as an input port ? v in = v dd 2.5 to 5.5 1 input high current i ih (3) cf1 v in = v dd 2.5 to 5.5 15 i il (1) ? ports 0, 1, 2 ? ports 3, 7, 8 ? ports a, b, c ? si2p00 to si2p03 ? res ? pwm0, pwm1 ? output disable ? pull-up resistor off ? v in = v ss (including the off-leak current of the output tr.) 2.5 to 5.5 -1 i il (2) xt1, xt2 ? using as an input port ? v in = v ss 2.5 to 5.5 -1 input low current i il (3) cf1 v in = v ss 2.5 to 5.5 -15 a v oh (1) ? ports 0, 1, 2, 3 ? ports b, c i oh = -1.0ma 4.5 to 5.5 v dd -1 v oh (2) ? si2p00 to si2p03 ? pwm0, pwm1 i oh = -0.1ma 2.5 to 5.5 v dd -0.5 v oh (3) i oh = -5.0ma 4.5 to 5.5 v dd -1 v oh (4) port a i oh = -0.4ma 2.5 to 5.5 v dd -0.5 output high voltage v oh (5) ports 71, 72, 73 i oh = -0.4ma 4.5 to 5.5 v dd -1 v ol (1) i ol = 10ma 4.5 to 5.5 1.5 v ol (2) i ol = 1.6ma 4.5 to 5.5 0.4 v ol (3) ? ports 0, 1, 2, 3 ? ports b, c ? si2p00 to si2p03 ? pwm0, pwm1 i ol = 1ma 2.5 to 5.5 0.4 v ol (4) p00, p01 i ol = 30ma 4.5 to 5.5 1.5 v ol (5) 2.5 to 5.5 0.4 v ol (6) ports 7, 8 i ol = 1ma 2.5 to 5.5 0.4 v ol (7) i ol = 15ma 4.5 to 5.5 1.5 output low voltage v ol (8) port a i ol = 2ma 2.5 to 5.5 0.4 v pull-up resistor rpu ? ports 0, 1, 2, 3 ? port 7 ? ports a, b, c v oh = 0.9v dd 2.5 to 5.5 15 40 70 k ? hysteresis voltage vhis ? res ? port 1 ? port 2 ? port 7 ? sip00 to sip03 2.5 to 5.5 0.1v dd v pin capacitance cp all pins ? all pins except the measured terminal : v in = v ss ? f = 1mhz ? ta = 25c 2.5 to 5.5 10 pf
LC87F54C8A no.7851-15/25 serial input/output characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit cycle tsck(1) 2 tsckl(1) 1 low level pulse width tsckla(1) 1 tsckh(1) 1 high level pulse width tsckha(1) sck0 (p12), si2p2 refer to figure 6 2.5 to 5.5 4 (sio0) 5 (sio2) cycle tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1 (p15) refer to figure 6 2.5 to 5.5 1 cycle tsck(3) 4/3 tcyc tsckl(3) ? cmos output ? refer to figure 6 1/2 sck0 (p12) sio0 3/4 low level pulse width tsckla(2) si2p2, si2p3 sio2 1 tsckh(3) 1/2 sck0 (p12) sio0 2 high level pulse width tsckha(2) sck0 (p12), si2p2 si2p3 si2p2, si2p3 sio2 2.5 to 5.5 7/4 tsck cycle tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1 (p15) ? cmos output ? refer to figure 6 2.5 to 5.5 1/2 tsck data set-up time tsdi 0.03 serial input data hold time thdi sb0 (p11), sb1 (p14), si2p1 si0, si1 ? data set-up to si0clk ? data hold from si0clk ? refer to figure 6 2.5 to 5.5 0.03 serial output output delay time tdd0 so0 (p10), so1 (p13), sb0 (o11), sb1 (p14), si2p0, si2p1 ? data hold from si0clk ? time delay from si0clk trailing edge to the so data change in the open drain ? refer to figure 6 2.5 to 5.5 1/3tcyc +0.05 s
LC87F54C8A no.7851-16/25 parallel input/output characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v note : if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. refer to figures 8 and 9 for parallel output timing. limits parameter symbol pins conditions v dd [v] min typ max unit write cycle, read cycle tc(1) 2.5 to 5.5 1 tcyc tsa(1) ? wr (pa3), pb0 to pb7 ? rd (pa4), pc0 to pc7 2.5 to 5.5 1/3tcyc -30ns address set-up time tsa(2) rd (pa4), pc0 to pc7 from address set-up until control signal changes 2.5 to 5.5 2/3tcyc -30ns tha(1) rd (pa4), pc0 to pc7 from change of rd until address change 2.5 to 5.5 1/6tcyc tcyc & ns address hold time tha(2) wr (pa3), pc0 to pc7 from change of wr until address change 2.5 to 5.5 5 ns tsrs(1) wr (pa3), rs(pa5), cs (pax) from change of rs, cs until change in wr 2.5 to 5.5 1/6tcyc -15ns tsrs(2) rd (pa4), rs(pa5) 2.5 to 5.5 1/6tcyc -15ns rs set-up time tsrs(3) rd (pa4), rs(pa5) from change of rs until change in rd 2.5 to 5.5 1/3tcyc -15ns tscs(1) rd (pa4), cs (pax) from change in cs until change in rd 2.5 to 5.5 1/3tcyc -15ns cs set-up time tscs(2) wr (pa3), cs (pax) from change in cs until change in wr 2.5 to 5.5 2/3tcyc -15ns tcyc & ns thrs(1) wr (pa3), rs(pa5) from change in wr until change in rs 2.5 to 5.5 0 ns thrs(2) rd (pa4), rs(pa5), cs (pax) 2.5 to 5.5 1/6tcyc tcyc & ns rs hold time thrs(3) rd (pa4), rs(pa5), cs (pax) from change in rd until change in rs, cs 2.5 to 5.5 0 ns thcs(1) rd (pa4), rs(pa5) from change in rd until change in cs 2.5 to 5.5 1/6tcyc tcyc & ns cs hold time thcs(2) wr (pa3), rs(pa5) from change in wr until change in cs 2.5 to 5.5 0 ns twrh(1) wr (pa3) 2.5 to 5.5 1/6tcyc -5ns 1/6tcyc wr "h" pulse width twrh(2) wr (pa3) 2.5 to 5.5 2/3tcyc -5ns 2/3tcyc twrl(1) wr (pa3) 2.5 to 5.5 1/6tcyc -5ns 1/6tcyc wr "l" pulse width twrl(2) wr (pa3) 2.5 to 5.5 1/3tcyc -5ns 1/3tcyc trdh(1) rd (pa4) 2.5 to 5.5 1/6tcyc -5ns 1/6tcyc rd "h" pulse width trdh(2) rd (pa4) 2.5 to 5.5 1/3tcyc -5ns 1/3tcyc trdl(1) rd (pa4) 2.5 to 5.5 1/3tcyc -5ns 1/3tcyc rd "l" pulse width trdl(2) rd (pa4) 2.5 to 5.5 1/2tcyc -5ns 1/2 tcyc tcyc & ns continued on next page.
LC87F54C8A no.7851-17/25 continued from preceding page. limits parameter symbol pins conditions v dd [v] min typ max unit tddt(1) rd (pa4), pb0 to pb7 2.5 to 5.5 1/6tcyc -15ns data write maximum delay tddt(2) rd (pa4), pb0 to pb7 the time delay allowed, from rd leading edge until input data set-up (note 1) 2.5 to 5.5 1/3tcyc -15ns tcyc & ns input data set-up time tsdtr(1) rd (pa4), pb0 to pb7 from input data set-up to rd leading edge. (note 2) 2.5 to 5.5 40 input data hold time thdtr(1) rd (pa4), pb0 to pb7 from rd leading edge until input data hold 2.5 to 5.5 0 ns tsdtw(1) rd (pa4), pb0 to pb7 2.5 to 5.5 1/3tcyc -30ns output data set-up time tsdtw(2) rd (pa4), pb0 to pb7 from output data set-up until wr leading edge 2.5 to 5.5 1/3tcyc -30ns tcyc & ns thdtw(1) 2.5 to 5.5 0 output data hold time thdtw(2) rd (pa4), pb0 to pb7 from wr leading edge until output data hold 2.5 to 5.5 0 ns note 1 : time until incorrect data of low disappears. note 2 : incorrect data of low is not output in the period between trdl(1) to tddt(1). pulse input conditions / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) int0 (p70), int1 (p71), int2 (p72) int4 (p20 to p23) int5 (p24 to p27) ? interrupt acceptable ? timer 0 and 1 event input acceptable 2.5 to 5.5 1 tpih(2) tpil(2) int3 (p73) (the noise rejection clock is selected to 1/1.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 2 tpih(3) tpil(3) int3 (p73) (the noise rejection clock is selected to 1/32.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 64 tpih(4) tpil(4) int3 (p73) (the noise rejection clock is selected to 1/128.) ? interrupt acceptable ? timer 0 event input acceptable 2.5 to 5.5 256 tcyc high/low level pulse width tpil(5) res reset acceptable 2.5 to 5.5 200 s ad converter characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 2) 3.0 to 5.5 1.5 lsb ad conversion time = 32 tcyc (adcr2 = 0) (note 3) 3.0 to 5.5 15.10 (tcyc = 0.588 s) 97.92 (tcyc = 3.06 s) conversion time tcad ad conversion time = 64 tcyc (adcr2 = 1) (note 3) 3.0 to 5.5 15.10 (tcyc = 0.294 s) 97.92 (tcyc = 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain = v dd 3.0 to 5.5 1 analog port input current iainl an0 (p80) to an7 (p87) an8 (p70) an9 (p71) an10 (xt1) an11 (xt2) vain = v ss 3.0 to 5.5 -1 a note 2 : absolute precision excludes the quantizing error (1/2 lsb). note 3 : the conversion time is the time from executing the ad conversion instruction to setting the complete digital conversion value in the register.
LC87F54C8A no.7851-18/25 current dissipation characteristics / ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit iddop(1) ? fmcf = 10mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? 1/1 divided 4.5 to 5.5 18 35 iddop(2) ? cf1 = 20mhz by external clock ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? 1/2 divided 2.5 to 5.5 18 35 iddop(3) 4.5 to 5.5 9 15 iddop(4) ? fmcf = 5mhz by ceramic resonator ? fmx'tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops 2.5 to 4.5 6 11 iddop(5) 4.5 to 5.5 4 8 iddop(6) ? fmcf = 0hz (when oscillation stops) ? fmx'tal = 32.768khz by crystal oscillation ? system clock : rc oscillation 2.5 to 4.5 2 5 ma iddop(7) 4.5 to 6.0 80 200 current drain during basic operation (note 4) iddop(8) v dd 1 = v dd 2 = v dd 3 ? fmcf = 0hz (when oscillation stops) ? fmx'al = 32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops 2.5 to 4.5 40 150 a iddhalt(1) ? halt mode ? fmcf = 10mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (10mhz) ? internal rc oscillation stops ? 1/1 divided 4.5 to 5.5 6 12 iddhalt(2) ? halt mode ? cf1 = 20mhz by external clock ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf1 oscillation (20mhz) ? internal rc oscillation stops ? 1/2 divided 4.5 to 5.5 7 14 iddhalt(3) 4.5 to 5.5 3.3 5 iddhalt(4) ? halt mode ? fmcf = 5mhz by ceramic resonator ? fmx?tal = 32.768khz by crystal oscillation ? system clock : cf oscillation (5mhz) ? internal rc oscillation stops 2.5 to 4.5 1.5 3.2 iddhalt(5) 4.5 to 5.5 1 1.5 iddhalt(6) ? halt mode ? fmcf = 0hz (when oscillation stops) ? fmx?tal = 32.768khz by crystal oscillation ? system clock : rc oscillation 2.5 to 4.5 0.4 1 iddhalt(7) 4.5 to 5.5 60 150 current drain in halt mode (note 4) iddhalt(8) v dd 1 = v dd 2 = v dd 3 ? halt mode ? fmcf = 0hz (when oscillation stops) ? fmx'tal = 32.768khz by crystal oscillation ? system clock : x'tal oscillation (32.768khz) ? internal rc oscillation stops 2.5 to 4.5 20 72 ma 4.5 to 5.5 0.05 25 current drain during hold mode iddhold(1) v dd 1 ? hold mode ? cf1 = v dd or leave it open (when using external clock) 2.5 to 4.5 0.01 15 4.5 to 5.5 35 100 current drain during time- base clock hold mode iddhold(2) v dd 1 ? time-base clock hold mode ? cf1 = v dd or leave it open (when using external clock) ? fmx'tal = 32.768khz by crystal oscillation 2.5 to 4.5 15 45 a note 4 : the current of the output transist ors and pull-up mos transistors are excluded.
LC87F54C8A no.7851-19/25 f-rom write characteristics / ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v limits parameter symbol pins conditions v dd [v] min typ max unit on-board writing current iddfw(1) v dd 1 ? 128-byte writing ? including erase time current 4.5 to 5.5 30 65 ma writing time tfw(1) ? 128-byte writing ? including data erase time ? excluding time to fetch 128 byte data 4.5 to 5.5 5.0 10.0 ms main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 1. recommended circuit parameters for the main system clock using the ceramic resonator recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max note murata csls100g53 (15pf) (15pf) 100 ? 3.0 to 6.0v 0.04ms 0.40ms internal c1, c2 10mhz kyocera kbr-10.0m (24pf) (24pf) 0 ? 3.5 to 6.0v 0.02ms 0.20ms murata cstls4m00g53b (30pf) (30pf) 220 ? 2.5 to 6.0v 0.04ms 0.40ms internal c1, c2 4mhz kyocera pbrc4.00hr (33pf) (33pf) 1.0k ? 3.5 to 6.0v 0.02ms 0.20ms *the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions : 1. using the standard oscillation evaluation board sanyo has provided. 2. using the external peripheral parts with the indicated value. 3. the recommended circuit parameters for the peripheral parts are verified by the oscillator manufacturer. table 2. recommended circuit parameters for th e subsystem clock using the crystal oscillation recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max note 32.768khz seiko epson c-002rx 15pf 15pf open 300k ? 2.5 to 6.0v 0.8s 3s *the oscillation stabilizing time is the period until the oscillation becomes stable, after executing the instruction which starts the sub-clock oscillator or after releasing a hold mode. (refer to figure4)
LC87F54C8A no.7851-20/25 (notes) since the oscillation frequency precision is affected by the circuit pattern, place the oscillation related parts as close to the oscillation pins as possible, using the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1 0.5v dd
LC87F54C8A no.7851-21/25 reset time and oscillation stabilizing time hold release signal and oscillation stabilizing time figure 4 oscillation stabilizing time internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal no hold release signal hold release signal valid tmscf tmsxtal hold halt v dd limit power suppl y res internal rc oscillation cf1, cf2 xt1, xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution v dd gnd
LC87F54C8A no.7851-22/25 figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res v dd r res res (note) select c res and r res value to assure that at least 200 s reset time is generated after the v dd becomes higher than the minimum operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 si0clk : datain : dataout : dataout : datain : si0clk : dataout : datain : si0clk : tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0, 2) data ram transmission period (only sio0, 2)
LC87F54C8A no.7851-23/25 ? parallel input/output timing waveform : indirect setting, read mode note : if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. ? parallel input/output timing waveform : indirect setting, write mode note : if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. figure 8 indirect mode : parallel timing diagram tsrs(1) adr/data : cs : rs : wr : rd : datain : tc(1) rea d cyc l e tsa(1) addr thrs(1) twrh(1) twrl(1) tsrs ( 2 ) trdl(1) thrs(2) trdh(1) tsdtr(1) tddt(1) thdtr(1) data h adr/data : cs : rs : wr : rd : datain : tc(1) write cycle data addr tsa(1) tsrs(1) thrs(1) thdtw(1) thrs(3) tsrs(3) tsdtw(1) twrh(1) twrl(1) twrl(2)
LC87F54C8A no.7851-24/25 ? parallel input/output timing waveform : direct setting, read mode note : if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. ? parallel input/output timing waveform : direct setting, write mode note : if port a terminals will be used as rs, wr , rd or cs , then it should be set to cmos format by option data. figure 9 direct mode : parallel input/output timing diagrams data h tc(1) read cycle addr tsa(1) tscs ( 1 ) trdh(2) trdl(2) tddt ( 2 ) tsdtr(1) thdtr(1) tha(1) thcs(1) adr : cs : data : wr : rd : datain : tc(1) write cycle addr tsa ( 2 ) tscs ( 2 ) twrl(2) tsdtw(2) thdtw(2) tha(2) thcs(2) adr : cs : data : wr : rd : datain : data twrh(2)
LC87F54C8A no.7851-25/25 ps

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